This application claims priority to Korean Patent Application 2002-0026259, filed on May 13, 2002, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to semiconductor memory devices, and in particular to electrically programmable semiconductor memory devices.
A variety of different types of memory devices are known, including read only memory (ROM), read-write memory and erasable programmable ROM (EPROM). One particular type of EPROM that has proven desirable in various applications is electrically erasable PROM (EEPROM), which may be erased and programmed, but, unlike certain read-write memory, may be operated without needing to refresh data stored in the memory. There is also a trend toward enhancing the storage capacity and the density of integration in such memory devices. A NAND-type flash memory is one example of an EEPROM non-volatile semiconductor memory that may provide high capacity and integration density without the need for refreshing stored data.
FIG. 1 is a circuit diagram illustrating an exemplary memory cell array for a conventional NAND-type flash memory device. As shown in FIG. 1, a memory cell array 1 includes a plurality of memory cell strings 2 extending in a column direction of the memory cell array. Each of the strings 2 includes a string selection transistor SST, a ground selection transistor GST, and a plurality of memory cells, shown in FIG. 1 as sixteen (16) memory cells MC0-MC15 connected in series between the selection transistors SST and GST. A drain of the string selection transistor SST in each column is connected to a corresponding bit line, and its gate is connected to a string selection line SSL. A source of the ground selection transistor GST is connected to a common source line CSL and its gate is connected to a ground selection line GSL. Each of the memory cells MC0-MC15 is illustrated as a floating gate transistor that has a control gate, a floating gate, a source, and a drain. The control gates of the memory cells MC0-MC15 in each string are coupled to respective word lines WL0-WL15 defining the rows of the memory cell array.
NAND-type flash memory devices typically program memory cells commonly connected to a selected word line concurrently. However, with a flash memory device, it is generally not possible to successfully program selected memory cells within a single program cycle. A single program cycle is generally insufficient as memory cells may have different coupling ratios, for example, due to variability of process conditions or materials during manufacture of the memory device. For example, memory cells of a relatively larger coupling ratio are typically programmed more rapidly than those of a relatively smaller coupling ratio. Therefore, when memory cells of a relatively larger coupling ratio are programmed, remaining memory cells having a relatively smaller,coupling ratio may be maintained at an erased state.
For such memory devices, following a program operation, it is known to execute a verify operation to determine if the program operation was successful. However, due to the circuit configuration, the potential of the common source line CSL can be increased when the verify operation is carried out. For example, the potential of the common source line CSL may be raised due to the resistances R0-Rm of the common source line CSL and current ION0-IONm flowing through memory cell(s) of an erased state in each string. This effect may be referred to as xe2x80x9cCSL noise.xe2x80x9d As a result of the CSL noise, a memory cell having a threshold voltage programmed to a level lower than a verify or pass voltage may appear to meet the pass voltage level for its threshold during the verify operation. In Such a case, an insufficiently programmed memory cell could be seen as a sufficiently programmed memory cell during the verify operation.
By way of example, assume that a selected memory cell (e.g., MC0) is programmed up to a threshold voltage of about 0.3V and that the potential of the common source line CSL is raised by about 0.7V owing to current flowing through some of the memory cells during the verify operation. Under such conditions, the threshold voltage of the selected memory cell may be detected as exceeding 0.7V based on the raised potential of the common source line CSL. Thus, as illustrated in the graphical illustration of FIG. 2, after the program operation, threshold voltages of some of the memory cells can be distributed at voltage levels below the verify reference voltage Vref (e.g., about 0.7V) that corresponds to an off-cell. Therefore, when the program operation is completed, since memory cells having a threshold voltage of about 0.3V are at an under-program state, they may bee judged to be an on-cell during a read operation, resulting in a device failure.
In some embodiments of the present invention programmable memory devices include a memory cell having an associated bit line. A buffer circuit couples the bit line to a data line. The buffer circuit has a sense node coupled to the bit line and includes a latch circuit having a latch node coupled to the data line. A control circuit resets the latch node between a program operation of the memory cell and its corresponding program-verify operation. The memory devices may be NAND-type flash memory devices and the memory cell may be one of a string of memory cells connected in series between a bit line and a common source line. A transistor may couple the data line to the latch node and a transistor may couple the latch node to the sense node.
In other embodiments of the present invention, the latch circuit includes a first and a second latch circuit. The first latch circuit has a first latch node selectively coupled to a third latch node, which is the latch node of the buffer circuit coupled to the data line, and a second latch node selectively coupled to a first reference voltage. The second latch circuit is coupled to the third latch node and has a fourth latch node coupled to the first reference voltage by a select circuit. The select circuit is responsive to signals on the first latch node and the sense node.
In further embodiments of the present invention, the control circuit is configured to selectively couple the first latch node to the third latch node to latch data on the first latch node during a program operation. The second latch control circuit may be configured to latch the data to the third latch node during the program operation. The control circuit may be configured to maintain program-inhibit data at the third latch node when data on the first latch node or data on the sense node is program-inhibit data. In particular embodiments, the control circuit is configured to reset the first latch node during a read operation and/or to selectively discharge the first latch node responsive to data on the sense node during a read operation. The control circuit may be configured to match data on the third latch node to data on the first latch node after discharge of the sense node during the read operation.
In other embodiments of the present invention, methods for programming a programmable semiconductor memory device include programming a plurality of memory cells of the semiconductor memory device. Latched programming data presented to ones of the plurality of memory cells is reset. After resetting the latched program data, the programming of the plurality of memory cells is verified in a program-verify operation in a single program cycle. In particular embodiments of the present invention, the memory device is a NAND-type flash memory device and the plurality of memory cells include a plurality of strings of memory cells, each of the strings of memory cells being connected in series between a bit line of the memory device and a common source line of the memory device. Accordingly, various embodiments of the present invention may preclude or reduce the likelihood of memory cells being insufficiently programmed because of a raised potential on a common source line during program-verify operations.
In further embodiments of the present invention, semiconductor memory devices include a memory cell array having a plurality of bit lines, a plurality of word lines, and a plurality of memory cells arranged in a matrix of the word lines and the bit lines. A page buffer group has a plurality of page buffers and is connected to the bit lines of the memory cell array. A column-pass gate circuit is connected between the page buffer group and a data bus. Each of the page buffers may include a first transistor having a drain connected to a first node, a source, and a gate connected to receive a first control signal; a first latch having a first latch node connected to the source of the first transistor and a second latch node; a second transistor having a drain connected to a sensing node, a source connected to the first node, and a gate connected to receive a second control signal; a second latch having a third latch node connected to the source of the second transistor and the first node, and a fourth latch node; a third transistor having a drain connected to the fourth latch node, a source, and a gate connected to the sensing node; a fourth transistor having a drain connected to the fourth latch node, a source, and a gate connected to the first latch node; and a fifth transistor having a drain connected to the sources of the third and fourth transistors, a source grounded, and a gate connected to receive a third control signal.
The first control signal may be activated such that data to be programmed is latched at the first latch node when a program operation commences. The data to be programmed may be latched at the third latch node of the second latch. When a program-verify operation commences, the third and fourth latch nodes of the second latch may be reset. The third control signal may be activated such that program-inhibit data is maintained at the third latch node of the second latch when either one of data on the sensing node and data on the first latch node of the first latch is program-inhibit data.
In other embodiments of the present invention, each of the page buffers includes a sixth transistor having a drain connected to the second latch node of the first latch, a source grounded, and a gate connected to receive a fourth control signal. The page buffers further include a seventh transistor having a drain connected to the first latch node of the first latch, a source, and a gate connected to the sensing node and an eighth transistor having a drain connected to the source of the seventh transistor, a source grounded, and a gate connected to receive a fifth control signal.
The fourth control signal may be activated to reset the first latch node of the first latch when a normal read operation commences. The fifth control signal may be activated to selectively discharge the first latch node of the first latch, based on a logic level of the sensing node, during a normal read operation. The sensing node may be discharged into a ground voltage after the first latch node of the first latch is set according to a logic level of the sensing node during the normal read operation. Furthermore, the third control signal may be activated to establish the third latch node of the second latch into data on the first latch node of the first latch, after the sensing node is discharged, during the normal read operation.